1. Field of the Invention
The present invention relates to a driver circuit of a semiconductor display device (hereinafter referred to as display device), and to a display device using the driver circuit. More particularly, the present invention relates to a driver circuit of an active matrix display device having a thin film transistor (hereinafter referred to as TFT) formed on an insulator, and to an active matrix display device using the driver circuit. Of those, in particular, the present invention relates to a driver circuit of an active matrix display device input with a digital image signal and an active matrix display device using the driver circuit.
2. Description of the Related Art
Recently, the use of a display device in which a semiconductor thin film is formed on an insulator, in particular, a glass substrate, especially an active matrix display device using TFTs, is spreading. The active matrix display device using TFTs has several hundred thousands to several millions of TFTs arranged in matrix, and display of images is performed by controlling the charge of respective pixels.
Further, as a recent technique, in addition to a pixel TFT structuring a pixel, a technique relating to a polysilicon TFT where a driver circuit is simultaneously formed by using a TFT in the peripheral portion of a pixel portion is progressing.
Further, the driver circuit simultaneously formed here does not end in that deals with an analog image signal, but the driver circuit which deals with a digital image signal is realized.
A schematic diagram of a display device of a normal digital image signal input method is shown in FIG. 11. A pixel portion 1108 is arranged in the center. On the upper side of the pixel portion is arranged a source signal line driver circuit 1101 for controlling a source signal line. The source signal line driver circuit 1101 comprises a first latch circuit 1104, a second latch circuit 1105, a D/A converter circuit 1106, an analog switch 1107, and the like. On the left and right of the pixel portion, gate signal line driver circuits 1102 are arranged to control gate signal lines. Note that, in FIG. 11, the gate signal line driver circuits 1102 are arranged on both the left and right side of the pixel portion, but the circuit may be arranged on only one side. However, arrangement on both sides is more preferable from the point of view of driving efficiency and driving reliability.
The source signal line driver circuit 1101 is structured as shown in FIG. 12. This driver circuit is a source signal line driver circuit of the display device having a horizontal resolution of 1024 pixels and a 4 bit gray scale display capacity, and comprises a shift register circuit 1201 (SR), a first latch circuit 1202 (LAT1), a second latch circuit 1203 (LAT2), a D/A converter circuit 1204, and the like. Note that, FIG. 12 does not show the analog switch 1107 in FIG. 11. Further, a buffer circuit, a level shifter circuit or the like may be additionally arranged if necessary.
Further, throughout this specification, when specifically showing the circuit to sequentially output sampling pulses, it is written together as the shift register circuit, but in the present invention, the sampling pulse is not necessarily limited to be output by the shift register circuit.
The operations of the circuit is simply explained with reference to FIGS. 11 and 12. First, the shift register circuit 1201 is input with a clock signal (CLK), a clock inverted signal (CLKb) and a start pulse (S-SP), and the sampling pulses are sequentially output. The first latch circuit 1202 holds the respective digital image signals (digital data), with the input of the sampling pulses. In FIG. 12, since a 4 bit digital image signal is handled, in order to simultaneously hold data of each bit from the least significant bit to the most significant bit, the four first latch circuits operate simultaneously by the sampling pulse output from the shift register circuit of the first level. In the first latch circuits 1202, when the holding of the image signal for one horizontal period is completed, a latch signal (latch pulse) is input in a return line period, and the image signals held in the first latch circuits 1202 are all sent at once to the second latch circuits 1203.
Thereafter, a sampling pulse is again output from the first level of the shift register circuits 1201, and the holding of the image signal of the subsequent horizontal period starts. At the same time, the image signal held in the second latch circuit 1203 is input to the D/A converter circuit 1204, and converted to an analog signal. Here, the analog image signal is written in a pixel (not shown) through source signal lines (S0001 to S1024). By repeating this operation, the image is displayed.
FIG. 13 shows a portion of the source signal line driver circuit shown in FIG. 12. The sampling pulse is input to a first latch circuit 1302, a digital image signal for 1 bit is held, the holding of the digital image signal for one horizontal period is completed, and then the sampling pulse is transferred to a second latch circuit 1303 by the input of the latch signal (latch pulse). Here, the second latch circuit may have the same circuit structure as the first latch circuit.
By the way, the clock signal (CLK), the clock inverted signal (CLKb), the start pulse (S-SP), the digital image signal (digital data) and the latch signal (latch pulse) are all signals directly input from the outside, and an input at an arbitrary timing is possible. On the other hand, the timing of the pulse for holding the digital image signal depends on the timing of the sampling pulse output from a shift register circuit 1301. In order to hold the image signal normally, it is necessary that both of the timings match. However, since the sampling pulse has already passed a plurality of circuits, as shown in FIG. 2A, the sampling pulse in the timing chart shows only a delay indicated by 201. At first, the digital image signal is input in accordance with the sampling pulse of the timing chart, and therefore, in this state, the image signal may not be normally held. In this case, a slight adjustment of input timing of the digital image signal becomes necessary in accordance with the output of the actual pulse where delay has occurred.
Further, this delay time changes by variation of TFT characteristics structuring the circuit or the like, and thus, there are cases where it differs for each display apparatus. Therefore, every time there is a need for slight adjustments for each display apparatus.
In addition, with recent rapid high resolution and high precision of LCDs, the driving frequency of the whole driver circuit is getting higher. Therefore, in a case where only a slight delay occurs, there may be a case where the holding operation of the digital image signal may not be performed normally.
The present invention has been made in view of the above problems, and it is one of objects of the present invention to provide a driver circuit with a structure in which a sampling pulse delay does not influence the holding operation of a digital image signal.
In order to solve the above described objects, the following measures are taken in the present invention.
In the conventional example of the driver circuit shown in FIGS. 11 to 13, it is necessary to perform a slight adjustment of input timing of a digital image signal in accordance with the delay time of the sampling pulse. Further, since there is a variation for each display apparatus of the delay time, the slight adjustment had to be performed for each display apparatus.
Contrary to this, in the driver circuit of the present invention, a method in which the holding timing of a first latch circuit is directly determined by the signal input from the outside is taken, and the slight delay of the sampling pulse is made not to not influence the holding timing. In other words, even if there is a variation for each display apparatus, by inputting the holding timing signal and the digital image signal at the same time from the outside, both are always input to the circuit at predetermined timings, and a holding operation is always performed normally. Further, since the timing is not slightly adjusted in accordance with the delay of the circuit as conventionally, and the timing is matched and input in advance in the input stage of the plurality of signals, the adjustment becomes considerably easier.
Hereinbelow, a structure of the driver circuit of the display apparatus of the present invention will be described.
A driver circuit of a display device according to a first aspect of the present invention is characterized in that:
the driver circuit comprises:
a holding circuit performing holding of a digital image signal which is input;
a pre-charge circuit provided between a signal input portion of the holding circuit and a first power supply; and
a holding operation selection circuit provided between the signal input portion of the holding circuit and a digital image signal line, and that:
the pre-charge circuit is input with a pre-charge signal; and
the holding operation selection circuit is input with a sampling pulse, a multiplex signal, and a digital image signal.
A driver circuit of a display device according to a second aspect of the present invention is characterized in that:
the driver circuit comprises:
a holding circuit performing holding of a digital image signal which is input;
a pre-charge circuit provided between a signal input portion of the holding circuit and a first power supply; and
a holding operation selection circuit provided between the signal input portion of the holding circuit and a digital image signal line, and that:
the pre-charge circuit is input with a pre-charge signal;
the holding operation selection circuit is input with a sampling pulse, a multiplex signal and a digital image signal;
the pre-charge circuit, by the input of the pre-charge signal, makes the signal input portion of the holding portion and the first power supply in continuity; and
in the holding operation selection circuit, holding of the digital image signal is performed in the holding circuit, in a period where the input of the sampling pulse, the multiplex signal and the digital image signal overlap.
A driver circuit of a display device according to a third aspect of the present invention is characterized in that:
the driver circuit comprises:
a holding circuit performing holding of a digital image signal which is input;
a first transistor provided between a first power supply and a signal input portion of the holding circuit; and
second, third and fourth transistors provided serially between a second power supply and the signal input portion of the holding circuit, and that:
a gate electrode of the first transistor is input with a pre-charge signal;
a gate electrode of the second transistor is input with a multiplex signal;
a gate electrode of the third transistor is input with a digital image signal; and
a gate electrode of the fourth transistor is input with a sampling pulse.
A driver circuit of a display device according to a fourth aspect of the present invention is characterized in that:
the driver circuit comprises:
a holding circuit performing holding of a digital image signal which is input;
a first transistor provided between a first power supply and a signal input portion of the holding circuit;
second, third and fourth transistors provided serially between a second power supply and the signal input portion of the holding circuit, and that:
a gate electrode of the first transistor is input with a pre-charge signal;
the gate electrode of the second transistor is input with a multiplex signal;
the gate electrode of the third transistor is input with a digital image signal;
the gate electrode of the fourth transistor is input with a sampling pulse; and
the holding circuit performs holding of the digital image signal in a period where the input of the multiplex signal, the digital image signal and the sampling pulse overlap.
A driver circuit of a display device according to a fifth aspect of the present invention, in the third or fourth aspect of the invention, is characterized in that:
the first transistor is in continuity by the input of the pre-charge signal, and a potential of the signal input portion of the holding circuit takes a first power supply potential;
the multiplex signal and the digital image signal are input during the period that the sampling pulse is output, the second to fourth transistors are in continuity, and the potential in the signal input portion of the holding circuit changes to a second power supply potential; and
thereafter, until the next return line period, the second power supply potential is held in the holding circuit.
A driver circuit of a display device according to a sixth aspect of the present invention is characterized in that:
the driver circuit comprises:
a holding circuit performing holding of a digital image signal which is input;
first and second transistors arranged in parallel between a first power supply and a signal input portion of the holding circuit; and
third, fourth and fifth transistors arranged serially between a second power supply and the signal input portion of the holding circuit, and that:
a gate electrode of the first transistor is input with a pre-charge signal;
a gate electrode of the second transistor is applied with a second power supply potential;
a gate electrode of the third transistor is input with a multiplex signal;
a gate electrode of the fourth transistor is input with a digital image signal; and
a gate electrode of the fifth transistor is input with a sampling pulse.
A driver circuit of a display device according to a seventh aspect of the present invention is characterized in that:
the driver circuit comprises:
a holding circuit performing holding of a digital image signal which is input;
first and second transistors arranged in parallel between a first power supply and a signal input portion of the holding circuit; and
third, fourth and fifth transistors arranged serially between a second power supply and the signal input portion of the holding circuit, and that:
a gate electrode of the first transistor is input with a pre-charge signal;
a gate electrode of the second transistor is applied with a second power supply potential;
a gate electrode of the third transistor is input with a multiplex signal;
a gate electrode of the fourth transistor is input with a digital image signal;
a gate electrode of the fifth transistor is input with a sampling pulse; and
a holding circuit performs holding of the digital image signal in a period where the input of the multiplex signal, the digital image signal and the sampling pulse overlap.
A driver circuit of a display device according to an eighth aspect of the present invention, in the sixth or seventh aspect of the invention, is characterized in that:
the first transistor is in continuity by the input of the pre-charge signal, the potential in the signal input portion of the holding circuit takes a first power supply potential;
the multiplex signal and the digital image signal are input during the period that the sampling pulse is output, the third to fifth transistors are in continuity, and the potential in the signal input portion of the holding circuit changes to the second power supply potential; and
thereafter, until the next return line period, the second power supply potential is held in the holding circuit.
A driver circuit of a display device according to a ninth aspect of the present invention is characterized in that:
the driver circuit comprises:
a holding circuit performing holding of a digital image signal which is input;
a NAND circuit; and
an analog switch, and that:
the NAND circuit is input with a sampling pulse and a multiplex signal;
the holding circuit is input with a digital image signal through the analog switch;
the continuity and non-continuity of the analog switch is controlled by an output of the NAND circuit;
a write in of the image signal to the holding circuit is performed, with the continuity of the analog switch; and
thereafter, until the next return line period, the image signal is held in the holding circuit.
A driver circuit of a display device according to a tenth aspect of the present invention, in any one of the first to ninth aspects of the invention, is characterized in that the multiplex signal and the digital image signal are both directly input from the outside.
A driver circuit of a display device according to an eleventh aspect of the present invention, in any one of the first to tenth aspects of the invention, is characterized in that a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.
A driver circuit of a display device according to a twelfth aspect of the present invention, in any one of the first to eleventh aspects of the invention, is characterized in that the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.
A driver circuit of a display device according to a thirteenth aspect of the present invention, in any one of the first to eleventh aspects of the invention, is characterized in that the holding of the potential in the holding circuit is performed by a holding capacity.
According to a display device of a fourteenth aspect of the present invention, the display device characterized by using the driver circuit of the display device according to any one of the first to thirteenth aspects of the invention may be provided.